1. Field of the Invention
The present invention relates to a bootstrap circuit, and more particularly, to a bootstrap circuit applied in a bulk circuit using an N-channel Metal Oxide Semiconductor (NMOS) transistor as a power switch.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional bulk circuit 100 using an NMOS transistor as a power switch. As shown in FIG. 1, the bulk circuit 100 comprises a switch control circuit 100, a bootstrap circuit 120, a gate driving circuit GD, a transistor Q1, a diode D2, an inductor L1, two feedback resistors RFB1 and RFB2, and an output capacitor COUT. The transistor Q1 may be an NMOS transistor and is utilized as a power switch of the bulk circuit 100. The operational principle of the bulk circuit 100 is familiar to those skilled in the art and is not illustrated hereinafter for brevity.
The bulk circuit 100 is utilized for lowering down the voltage VIN (for example, 40 volts) provided by a DC voltage source VIN so as to generate a DC output voltage source VOUT to output a lowered DC voltage VOUT (for example, 35 volts). In addition, in FIG. 1, the voltage source VCC (for example, 7 volts) can be generated by the voltage source VIN through a Low Drop Out (LDO) regulator. The voltage source VSS is a ground end (providing voltage with 0 volt).
The gate driving circuit GD comprises two transistors Q2 and Q3. The transistors Q2 and Q3 are a PMOS transistor and an NMOS transistor respectively. The gate driving circuit GD is utilized for enhancing the signal outputted from the switch control circuit 110 so as to drive the transistor Q1. Furthermore, the gate driving circuit GD, in the FIG. 1, actually functions as an inverter.
The bootstrap circuit 120 comprises a diode D1 and an offset capacitor COS. It can be seen in FIG. 1 that the voltage VX and VY respectively on the nodes X and Y of the bootstrap circuit 120 are utilized as the bias voltages for the gate driving circuit GD.
The feedback resistors RFB1 and RFB2 are coupled in series to the output end of the bulk circuit 100 to form a voltage divider for providing a partial voltage of the output voltage VOUT as a feedback voltage VFB.
The switch control circuit 110 outputs the switch control signal SW1 according to the feedback voltage VFB. The switch control signal SW1 may be a Pulse Width Modulation (PWM) signal, wherein the duty ratio of the switch control signal SW1 is related to the feedback voltage VFB. The driving switch control signal SWD is obtained by the gate driving circuit GD enhancing the switch control signal SW1 so as to drive the transistor Q1, which means the enhanced switch control signal SW1 (the driving switch control signal SWD) is capable of turning on/off the transistor Q1. In addition, the switch control signal SW1 is inverted to the driving switch control signal SWD.
When the transistor Q1 is turned off, the power of the voltage source VIN is not conducted to the node Y, which means the voltage VY on the node Y is 0 volt or less at the time. Supposed that the forward voltage VD1 of the diode D1 is 0.7 volt, the voltage source VCC can charge the offset capacitor COS up to 6.3 volts by 7 volts (deducting the forward voltage VD1 of the diode D1).
When the transistor Q1 is turned on, the power of the voltage source VIN is conducted to the node Y, which means the voltage VY on the node Y is 40 volts at the time. Supposed that the forward voltage VD1 of the diode D1 is 0.7 volt and the offset capacitor COS has finished charging, the voltage VX on the node X is 46.3 volts. That is, the voltage range of the gate driving circuit GD capable of driving is from 40 volts to 46.3 volts. Therefore, at the time, supposed that the threshold voltage VTH1 of the transistor Q1 is 1.5 volts, the voltage on the gate of the transistor Q1 has to be more than 41.5 volts to turn on the transistor Q1. Since the voltage range of the gate driving circuit GD capable of driving is from 40 volts to 46.3 volts at the time, the transistor Q1 can be effectively turned on.
Consequently, by means of the bias voltages VX and VY that the bootstrap circuit 120 provides to the gate driving circuit GD, the switch control signal SW1 can effectively turn the transistor Q1 on or off by the gate driving circuit GD.
However, since the forward voltage of the diode is so high that when the transistor Q1 is turned on, the voltage range of gate driving circuit GD capable of driving is not wide enough to fully turn on the transistor Q1. In other words, for fully turning on the transistor Q1, the voltage VCC provided by the voltage source VCC must be high enough to fully turn on transistor Q1. However, since, in the modern fabrication, the size of the circuit elements on the wafer is becoming smaller and smaller, the voltage the circuit elements on the wafer can withstand is becoming lower and lower. Thus, if the voltage source VCC is too high, the circuit elements on the wafer are easily to be damaged. In this condition, either, for protecting the circuit elements on the wafer, the voltage source VCC has to be low enough, causing the transistor Q1 not to be fully turned on, or, for fully turning on the transistor Q1, the voltage source VCC has to be high enough, easily damaging the circuit elements on the wafer. Both methods are not convenient.